1. Field of the Invention
The present invention relates to voltage regulator and in particular to a low drop-out voltage regulator with low power dissipation.
2. Description of the Related Art
Currently, the increasing demand for higher performance power supply circuits has resulted in a continued development of voltage regulator devices. Many low voltage applications, such as for use in cell phones, pagers, laptops, camera recorders and other mobile battery operated devices, require the use of low drop-out (LDO) voltage regulators. These portable electronics applications typically require low voltage and small quiescent current flow to increase the battery efficiency and longevity.
The LDO voltage regulators generally can provide a well-specified and stable DC voltage whose input to output voltage difference is low. The LDO voltage regulators are usually configured for providing the power requirements to electrical circuits. The LDO voltage regulators typically have an error amplifier, and a pass device, e.g., a power transistor. These two components are coupled in series. The error amplifier is coupled to an input terminal of the LDO voltage regulators, and the pass device is coupled to an output terminal of the LDO voltage regulators. The pass device can then drive an external load.
In general, a feedback circuit is further provided to the LDO voltage regulators scaling the output voltage down and feeding back a scaled down voltage to the error amplifier. The LDO voltage regulators can further incorporate a compensation circuit to form a control loop and to provide Miller compensation in order to improve the stability of the LDO voltage regulators.
The pass device also introduces a large parasitic capacitance to the LDO voltage regulator. The large parasitic capacitance between a gate terminal of the pass device and the AC ground, for example 100 pF or more, can limit the capability of the error amplifier, since the parasitic capacitance needs to be charged or discharged during a certain period in order to restore the output voltage of the LDO voltage regulator to a constant value. The performance of the LDO voltage regulator is, therefore, greatly limited by the speed of the parasitic capacitance being charged and discharged which is defined a slew rate. Additionally, the presence of the large parasitic capacitance can produce a significant pole in the frequency response of the error amplifier, which can result in the error amplifier more difficult to be stable. The large parasitic capacitance in the pass device usually requires the configuration of a buffer, for example, a source follower or a unity-gain buffer, to isolate the high output resistance of the gain stage of the error amplifier from the large parasitic capacitance.
Conventionally, a dynamic bias circuit is inserted at a slew-rate limited node to provide an improved transient response performance. However, the insertion of the dynamic bias circuit can increase the complexity of the LDO voltage regulator. The insertion of the dynamic bias circuit may also create stability problems and cause the design of the LDO voltage regulator to become more complex. In addition, the LDO voltage regulator generally has a lower efficiency due to a higher ground current consumed by the dynamic bias circuit.
It is thus desirous to have an apparatus and method that can provide a stable output voltage with a higher slew rate and simple configuration when the capacitance of a load varies in a larger range and at the same time output a corresponding current with low power dissipation, high driving capacity and good stability. It is to such an apparatus and method the invention is primarily directed.